1. Field of the Invention
The present invention relates to static semiconductor memory devices and manufacturing methods thereof, and more specifically, to a structure of a memory cell for storing one-bit information in a static semiconductor memory device and a manufacturing method thereof.
2. Description of the Background Art
FIG. 26 shows an equivalent circuit of a memory cell in a static semiconductor memory device. With reference to FIG. 26, n type MOS (Metal Oxide Semiconductor) transistors (driver transistors) Q1 and Q2, p type MOS transistors (load transistors) Q3 and Q4, and n type MOS transistors (access transistors) Q5 and Q6 are formed within the memory cell in the static semiconductor memory device.
N type MOS transistors Q1 and Q2 are connected between a ground line (GND line) and a pair of storage nodes of the memory cell. P type MOS transistors Q3 and Q4 are connected between a power supply line (Vcc line) and the pair of storage nodes. N type MOS transistors Q5 and Q6 have source/drain terminals connected between one of a pair of bit lines BIT and /BIT, and one of the pair of storage nodes of the memory cell. The gates of n type MOS transistors Q5 and Q6 are connected to a word line.
FIGS. 27 and 28 are plan views showing an example of a memory cell in a conventional static semiconductor memory device having the above mentioned structure. It is noted that the structure is separated into plan views in FIGS. 27 and 28 for the convenience of description, as the memory cell in the static semiconductor memory device includes multiple layers. Also, in FIGS. 27 and 28, the region surrounded by a dotted line is a region for the one-bit memory cell. Memory cells are two-dimensionally arranged in a manner symmetrically folded at each side of the region, a side defining a boundary of the region, to form a memory array.
As shown in FIG. 27, formed in the main surface of a silicon substrate (not shown) is an n well region 24, within which p type MOS transistors (load transistors) Q3 and Q4 are formed. N type MOS transistors (driver transistors) Q1 and Q2 as well as n type MOS transistors (access transistors) Q5 and Q6 are formed outside n well region 24.
Access transistors Q5 and Q6 include n.sup.+ impurity diffusion regions 1a1 and 1b1 as well as 1a2 and 1b2, respectively. A polysilicon layer 2a functions as a gate for access transistors Q5 and Q6. Driver transistors Q1 and Q2 include n.sup.+ impurity region regions lc1 and lb1 as well as 1c2 and 1b2, respectively. Further, load transistors Q3 and Q4 have p.sup.+ impurity diffusion regions 8a1 and 8b1 as well as 8a2 and 8b2, respectively.
A polysilicon layer 2b1 functions as a gate for driver transistor Q1 and load transistor Q3, whereas a polysilicon layer 2b2 functions as a gate for driver transistor Q2 and load transistor Q4. Polysilicon layer 2b1 is electrically connected to n.sup.+ impurity diffusion region 1b2 through a contact hole 3d2, while polysilicon layer 2b2 is connected to p.sup.+ impurity diffusion region 8b1 through a contact hole 3d1. The connection corresponds to a storage node portion.
N.sup.+ impurity diffusion regions 1a1 and 1a2 are connected to a bit line through contact holes 3a1 and 3a2. N.sup.+ impurity diffusion regions 1c1 and 1c2 are connected to a ground line through contact holes 3b1 and 3b2. P.sup.+ impurity diffusion regions 8a1 and 8a2 are connected to a power supply line through contact holes 3c1 and 3c2.
Referring now to FIG. 28, first metal interconnections 5a1, 5a2, 5b1, 5b2, 5c, 5d1 and 5d2 are formed on the structure shown in FIG. 27 with an insulation layer interposed. Second metal interconnections 7a1, 7a2, 7b1 and 7b2 are formed on these first metal interconnections with an insulation layer interposed. 7a1 and 7a2 as well as 7b1 and 7b2 correspond to the bit and ground lines, respectively.
First metal interconnections 5a1 and 5a2 are respectively connected to second metal interconnections 7a1 and 7a2 through via holes 6a1 and 6a2. First metal interconnection 5b1 is connected to second metal interconnection 7b1 through via hole 6b1, whereas second metal interconnection 5b2 is connected to second metal interconnection 7b2 through via hole 6b2.
First metal interconnection 5d1 is connected to n.sup.+ and p.sup.+ impurity diffusion regions 1b1 and 8b1 through contact holes 3e1 and 3d1, whereas first metal interconnection 5d2 is connected to n.sup.+ and p.sup.+ impurity diffusion regions 1b2 and 8b2 through contact holes 3d2 and 3e2. First metal interconnection 5c is connected to p.sup.+ impurity diffusion regions 8a1 and 8a2 through contact holes 3c1 and 3c2.
Referring now to FIG. 29, the cross sectional structure along line 29--29 in FIGS. 27 and 28 will be described. With reference to FIG. 29, n and p wells 24 and 25 are formed in the main surface of silicon substrate 11. Further, an isolation region 14 is selectively formed in the main surface of silicon substrate 11. P.sup.+ impurity diffusion region 8b1 is formed in the surface of the n well, and n.sup.+ impurity diffusion regions 1a1 an 1b1 are formed in the surface of the p well spaced apart from each other.
Polysilicon layers 2a and 2b2 are formed on the main surface of silicon substrate 11 with gate insulation layers 16a and 16b interposed, respectively. Polysilicon layer 2b1 also extends over isolation region 14. An interlayer insulation layer 17a is formed to cover polysilicon layers 2a, 2b1 and 2b2. Contact holes 3a1, 3e1 and 3d1 are formed in interlayer insulation layer 17a.
First metal interconnections 5a1 and 5d1 are formed on interlayer insulation layer 17a. An interlayer insulation layer 17b is formed to cover first metal interconnections 5a1 and 5d1. Via hole 6a1 is formed in interlayer insulation layer 17b. Second metal interconnection 7a1 is formed on interlayer insulation layer 17b.
The conventional memory cell having the aforementioned structure is however encountered with the following problems. As shown in FIG. 29, a boundary of n and p wells 24 and 25 exists between the nMOS and pMOS transistors, and therefore the nMOS and pMOS transistors or the like must be formed a distance apart from the boundary, which disadvantageously increases the memory cell region.
In addition, as the nMOS and pMOS transistors must be formed a distance apart from the above mentioned boundary, the number of boundaries in the memory cell is desirably minimized. For this reason, MOS transistors of the same conductivity types are combined together as shown in FIG. 27. As a result, for example in the case shown in FIG. 27, an upper layer interconnection, such as first metal interconnection 5d1, for connecting p.sup.+ impurity diffusion region 8b1 to n.sup.+ impurity diffusion region 1b1 is required, thereby increasing the number of interconnections. Moreover, the disadvantageous increase in the number of interconnections results in a complicated interconnection structure.